1. Field of the Invention
The present invention relates to a fan-out package of a wafer level and a method for manufacturing the same.
2. Discussion of Related Art
In recent years, according to the rapid development of the electronic industries, various techniques have been developed in the fields of electronic devices and circuit boards. In particular, electronic products tend to be lighter and smaller and to have multifunction and high performance, so that integrated circuit packaging technologies have been required according to these tendencies.
The integrated circuit packaging refers to things which form signal input/output terminals toward a main board using a lead frame or a PCB (printed circuit board) and are molded using an encapsulant, in order to optimize and maximize the electrical performance of a semiconductor chip.
Such integrated circuit packaging protects a semiconductor chip such as a single device, an integrated circuit, or the like which is formed in such a manner that a variety of electronic circuits and wiring are laminated, from various external environments, for example, dust, moisture, electrical and mechanical load, and the like.
Meanwhile, in the past, chips in a wafer form are separated one by one and then subjected to a packaging step to be used, and traditionally, a packaging method such as QFP (quad flat package), CSP (chip scale package), BGA (ball grid array), or the like has been used.
In a case in which the packaging is performed by separating the chips in this manner, each chip should be treated individually. Accordingly, when performing a patterning operation or the like, a problem in the alignment of the chips may occur, and the sizes of the chips tend to be gradually smaller, and thereby it is difficult to treat the individual chips.
In order to overcome these problems, a WLP (wafer level packaging) is used. The WLP is a technique in which packaging proceeds on the whole chips without separating the chips from the wafer or the individual chips are rearranged in a wafer form and then packaging proceeds, packaging is completed through the above-described method, and then the chips are subjected to a dicing step for cutting the completed packaging one by one in units of the individual chips and used. Through this, the packaging step may be simplified and the chip size obtained after performing the packaging may be also miniaturized, and thereby an area in which the chips are mounted on the PCB is also reduced so that a semiconductor assembly process is dramatically improved.
Through such WLP, the size of the package may be reduced, and a CSP (chip scale package) having a substantially similar size to the latest chip size has been developed.
However, in recent years, as the mobile markets such as smart phones, tablet PCs, portable game devices, and the like are expanded, the chip size is required to be further smaller. In contrast, the number of input/output (I/O) terminals of the chips tends to increase rather than decrease. Accordingly, there is a limitation in meeting this requirement when using a fan-in package such as the existing CSP or the like.
In the conventional CSP, the arrangement of solder balls for input and output is not larger than the chip size, so this was referred to as the fan-in package. However, the latest chip size is gradually miniaturized, whereas the number of I/O terminals of the chips remains as is or rather increases for the purpose of performance improvement. Accordingly, there arises a case in which the fan-in package is not able to afford the increasing number of I/O terminals, that is, the number of solder balls.
In order to address this problem, a WLP in which an area where the solder balls are arranged is larger than the chip size has been developed, and this is referred to as a fan-out WLP.
FIGS. 1A to 1E are views showing a process of manufacturing a WLP according to the related art.
First, referring to FIG. 1A, bottom surfaces of individual chips 10 separated from a wafer state are attached on a top surface of a carrier wafer 12 (or mold frame) at predetermined intervals using a double-sided adhesive tape 11.
Next, as shown in FIG. 1B, the individual chips 10 are all molded with a molding compound resin 20 at the same time, and the molding compound resin 20 having a predetermined thickness encapsulates top surfaces and side surfaces of the individual chips 10.
Next, as shown in FIG. 1C, when the molding compound resin 20 containing the individual chips 10 is removed from an adhesive surface of the carrier wafer 12, the bottom surfaces of the individual chips are exposed to the outside. Next, a grinding step proceeds so that upper and bottom surfaces of the molding compound resin 20 becomes even surfaces, and a cleaning step for the bottom surfaces of the chips proceeds.
Next, as shown in FIG. 1D, a process for forming an RDL (redistribution layer) 30 which is a kind of metal wiring line and bumps 40 proceeds from bonding pads of the individual chips 10 to a desired position of the bottom surface of the molding compound resin 20.
The RDL refers to a metal wiring line that extends outward from the bonding pad so that I/O terminals are attached with wider intervals. In a case in which the I/O terminals such as solder balls are attached on the bonding pads of the individual chips which form a fine pitch therebetween, the RDL may solve electric short phenomena which occur because the I/O terminals are brought into contact with each other.
In this instance, typically, a passivation layer is formed on the surface except the bonding pads of the chips, and the RDL is formed on the formed passivation layer by a plating step. Next, an insulating passivation layer for preventing short phenomena between the RDLs while blocking moisture, various foreign substances, and the like from penetrating into the RDL is formed on the formed RDL, and description of the specific formation process will be omitted.
Finally, as shown in FIG. 1E, a process in which sawing is performed along a sawing line (each package boundary line of the molding compound resin) proceeds. Thus, individual wafer level fan-out packages including the individual chips 10, the molding compound resin 20 formed in the peripheries of the chips, the lower RDL 30, the bumps 40, and the like are completed.
However, in a case of a process for manufacturing a wafer level package according to the related art, individual dies on the sawn wafer are attached on the carrier, and then an encapsulation step proceeds. In this instance, steps from the encapsulation step to a step before a bumping step proceeds are considerably long, so that a process lead time is long, resulting in a reduction in the yield and an increase in the costs.
In addition, the related art has a single package structure so there is a limit to apply various applications thereto. The molding compound resin may act as the wafer, and therefore warpage of the fan-out package occurs frequently upon the bumping step, and cracks are generated when the warpage is severe.
In addition, the wafer level package according to the related art has the single package structure, so it is difficult to configure packages in various forms.
Meanwhile, in such a semiconductor package, a heat dissipating means for dissipating, to the outside, heat generated from the inside of the package upon operation of the package is generally employed. That is, the characteristics of a semiconductor device in the form of die are sensitively changed according to moisture, temperature, and the like.
Thus, when the semiconductor device generates a lot of heat while being operated, a means for effectively radiating heat generated from the inside in a process in which semiconductor dies are processed and assembled into the semiconductor package is employed.
However, in the related art, in a case of a semiconductor package to which a heat spreader is attached, the heat spreader is attached for each unit, and thus there is a problem that the processing time becomes longer.
In this regard, in Korean Patent Application No. 10-0666919 (Title: Adhesive sheet for semiconductor package, semiconductor device having the same, multi-stack package having the same, and method for manufacturing the semiconductor device and method for manufacturing the multi-stack package), an adhesive sheet for a semiconductor package which includes an adhesive layer that is adhered to a bottom surface of a semiconductor chip; a deformation suppression layer that is embedded in the adhesive layer to suppress deformation of the semiconductor chip; and a base film that is formed on a bottom surface of the adhesive layer is disclosed.
In addition, in Korean Patent Laid-Open Publication No. 10-2008-0102641 (Title: Semiconductor package having heat spreader), a semiconductor package which includes a semiconductor chip in which a pad is formed; a metal pattern for a RDL that connects the pad to a solder ball; a heat spreader to which the semiconductor chip is attached; and an insulating layer that is laminated on the heat spreader to seal the semiconductor chip and in which the metal pattern for the RDL is disposed and the solder ball is formed is disclosed. Here, for a fan-out structure, an area of the heat spreader and an area in which the solder ball is disposed are larger than an area of the semiconductor chip, and the heat spreader is made of a metallic material.